1. Field of the Invention
The present invention relates to a clock generator having a phase-locked-loop (PLL) and a method of generating a clock, and more particularly to a PLL-based clock generator with one pole that is able to improve a period jitter characteristic and a method of generating a clock using the same.
2. Related Art
A clock generator is a device that provides a clock signal to various digital systems. FIG. 1 is a schematic block diagram which illustrates a conventional PLL-based clock generator using a voltage-controlled oscillator (VCO) 40. Referring to FIG. 1, the output of the VCO 40 is sampled in a sampler 50 and changed to a signal FFEED having a low frequency in a divider 60. The signal FFEED is applied to a phase detector 10. The output signal PDET from the phase detector 10 is applied to a charge pump 20, which generates a signal LCV, which is applied to a loop filter 30. The output of the loop filter is applied to the VCO 40, and the output of the VCO PCLK is fed back through the sampler 50 and the divider 60 to an input terminal of the phase detector 10. The output signal FFEED of the divider 60 is inputted to one input terminal of the phase detector 10. The clock input signal FIN is inputted to another input terminal of the phase detector 10. The output of the phase detector 10 is changed to a loop control signal LCV, and is inputted to the loop filter 30. The loop filter 30 sets a bandwidth of the circuit, and the output of the loop filter 30 is inputted to an input terminal of the VCO 40.
The conventional clock generator shown in FIG. 1 has two poles. One of the two poles is generated by a capacitor (not shown) in the loop filter 30, and the other is generated at the output of the VCO 40.
The 2-pole system is unstable, and needs to be stabilized by adding a zero in the loop filter 30. However, stabilizing the system using this method may deteriorate the period jitter characteristic of the circuit.
There are two methods for preventing the deterioration of the period jitter characteristic. One is to design a clock generator based on a delay-locked loop (DLL), and the other is to design a clock generator based on PLL of which the cycling nature is compensated.
Referring to FIG. 1, the pole generated by the loop filter 30 is necessary to change the ac signal to dc signal and control the VCO 40. The pole at the output terminal of the VCO 40 is generated because the frequency of the output of the VCO 40 is compared in the phase detector 10 in the form of phase. The phase of the pole at the output terminal of the VCO 40 is represented as an integration form of frequencies.
A method to design a clock generator based on DLL uses a voltage-controlled delay line (VCDL) instead of VCO. In this method, the pole is only generated by the capacitor comprising the loop filter because the phase is compared and controlled. Thus, a one-pole system can be implemented in this method. However, there is a limit in applying this method to wide range of frequencies.